AMD D2D Interconnect in "Zen 6" Receives Sea-of-Wires Enhancement

AMD Explores Parallel Die-to-Die Interconnects for Next-Generation APUs

Recent insights from the High Yield YouTube channel indicate that AMD is shifting its approach to die-to-die interconnects, moving away from traditional SERDES-based links in favor of a wide, parallel "sea-of-wires" architecture. This transition is becoming evident in early images of the Strix Halo APU, where a rectangular pad field—suggestive of fan-out packaging—replaces the large SERDES blocks previously found at the edges of compute dies (CCDs).

The absence of these SERDES blocks, combined with packaging features that align with TSMC’s InFO-oS technology, points to AMD experimenting with dense parallel traces. This design allows fabric lanes to traverse the package directly, rather than being funneled through a limited number of high-speed serial links. Traditionally, serializing and deserializing data at each package boundary introduces power overhead and latency due to the need for clock recovery, equalization, and data encoding/decoding.

Benefits of Wide Parallel Interconnects

Engineering Challenges and Future Potential

While the parallel "sea-of-wires" approach offers clear advantages in bandwidth and latency, it introduces new engineering challenges. Routing a high density of parallel traces beneath a die raises concerns around signal integrity, thermal management, and manufacturing complexity. Addressing these issues will require advanced multi-layer redistribution layer (RDL) design and close collaboration between die and packaging engineering teams.

If AMD successfully overcomes these hurdles and extends this technology to future architectures like Zen 6, the result could be substantial improvements in performance per watt and reduced latency for CPU workloads. Notably, a faster memory integrated memory controller (IMC) could be achieved, thanks to lower latency from the I/O die. This evolution in die-to-die interconnects underscores AMD’s commitment to pushing the boundaries of chiplet and packaging technology for next-generation computing.