TSMC Unveils Advanced HBM4 Technology and Packaging Innovations
At the recent Open Innovation Platform Ecosystem Forum in Amsterdam, TSMC shared new insights into its next-generation High Bandwidth Memory (HBM) solutions, specifically for the HBM4 era. According to reports from HardwareLUXX, TSMC’s custom C-HBM4E logic die will transition to the advanced N3P process node, accompanied by a voltage reduction from 0.8V to 0.75V. This strategic move is designed to deliver approximately double the power efficiency compared to current DRAM manufacturing processes.
TSMC also revealed that even standard HBM4 base dies will benefit from significant upgrades. Departing from the traditional DRAM process used in HBM3E, the company plans to fabricate HBM4 base dies on its N12 logic node. This shift will lower the operating voltage from 1.1V to 0.8V, which is expected to yield a 1.5× improvement in energy efficiency.
For the custom C-HBM4E variant, the enhancements go further. The base die will not only utilize the N3P node but will also integrate memory controllers directly into the memory stack. Traditionally, these controllers reside on the host system-on-chip (SoC), but TSMC’s approach brings them into the stack itself, necessitating a fully custom physical interface (PHY) design.
Expanding Advanced Packaging: CoWoS and Beyond
TSMC is also broadening its advanced packaging portfolio, introducing updated Integrated Fan-Out (InFO) and System-on-Wafer (SoW) options. However, the company’s CoWoS (Chip-on-Wafer-on-Substrate) technology remains the primary driver of growth. After expanding reticle sizes from 1.5× to 3.3× and enabling support for up to eight HBM chips, TSMC is now advancing toward CoWoS-L. This next-generation packaging will support up to 12 HBM3E or HBM4 stacks, targeting high-performance AI hardware in 2026. An even larger A16 generation is planned for 2027, further increasing integration capabilities.
Industry Adoption and Roadmap
TSMC’s custom HBM logic dies are attracting significant industry interest. Micron has chosen TSMC to manufacture the logic base die for its HBM4E products, with mass production scheduled for 2027. SK Hynix is also preparing its first custom HBM4E offerings, expected to launch in the second half of next year. According to the Korea Financial Times, SK Hynix will utilize TSMC’s 12nm process for mainstream server-grade HBM base dies, while leading-edge GPUs from NVIDIA and TPUs from Google will adopt the more advanced 3nm node.
These developments underscore TSMC’s leadership in both memory technology and advanced packaging, positioning the company at the forefront of next-generation AI and high-performance computing solutions.
