JEDEC Previews Next-Generation LPDDR6 Features for Data Center and AI Workloads

The JEDEC Solid State Technology Association, recognized globally for its leadership in microelectronics standards, has announced a preview of new features planned for the upcoming version of its JESD209‑6 LPDDR6 standard. Building on the foundation established by the JESD209‑6 specification released in July 2025, JEDEC’s JC‑42.6 Subcommittee is working to expand LPDDR6’s capabilities beyond traditional mobile applications, targeting data center and accelerated computing environments that demand power-efficient, high-capacity memory solutions.

Key Enhancements in the Upcoming LPDDR6 Standard

  • Narrower Per-Die Interface (x6) for Higher Capacities: The next LPDDR6 update introduces a non-binary interface width, expanding from x16 to x24 and adding x12 and a new x6 sub-channel mode. This innovation enables more memory die per package, resulting in higher memory capacities per component and per channel—an essential advancement for AI-scale memory requirements.
  • Flexible Metadata Carve-Out: A new flexible metadata carve-out is designed to minimize the impact on peak data throughput. This feature allows data center operators to balance user capacity and metadata needs, optimizing for specific reliability and performance requirements.
  • 512 GB Density on the Horizon: LPDDR6 is set to surpass the current density limits of LPDDR5 and LPDDR5X, with support for memory densities up to 512 GB. This capability is tailored to meet the growing memory demands of AI training and inference workloads.
  • LPDDR6 SOCAMM2 Module Standard in Development: JEDEC is developing a new LPDDR6-based SOCAMM2 module standard. This standard aims to continue the compact, serviceable module form factor and provide a clear upgrade path from existing LPDDR5X SOCAMM2 modules.
  • LPDDR6 Processing-in-Memory (PIM) Standard Nearing Completion: The association is finalizing a standard for LPDDR6 PIM technology, which integrates processing capabilities directly within the memory. LPDDR6 PIM is designed to reduce data movement between memory and compute, delivering higher inference performance and lower power consumption—key benefits for both edge and data center inference workloads.

Advancing Memory Technology for AI and Data Centers

These planned enhancements to the LPDDR6 standard reflect JEDEC’s commitment to addressing the evolving needs of AI, machine learning, and high-performance computing. By enabling higher memory capacities, improved energy efficiency, and advanced processing capabilities, the next generation of LPDDR6 is poised to play a critical role in supporting the future of data-intensive workloads.